1. Stats
  2. USPTO
  3. TC 2800
  4. Group 28XX
  5. Art Unit 2893
  6. Examiner Fernandes

Examiner Fernandes Errol V

2893-FERNANDES-ERROL-V

Employment Information

Art Unit:2893 — Active solid-state devices (e.g., transistors, solid-state diodes)
Group:28XX — Semiconductors B
Classes: 257 — Active solid-state devices (e.g., transistors, solid-state diodes)
438 — Semiconductor device manufacturing: process
324 — Electricity: measuring and testing
327 — Miscellaneous active electrical nonlinear devices, circuits, and systems
318 — Electricity: motive power systems
428 — Stock material or miscellaneous articles
Phone:(571) 270-7433
Email:errol.fernandes@uspto.gov
Location:VA 22314
Title:Pat Examnr Elctrl Engrg
Service:18 years
Grade:GS-14

Grant Rate and Difficulty Ranking

4
3-Year Grant rate: 96% over 484 cases
Difficulty: Extremely Easy
Difficulty Percentile: 4th

With Examiner Fernandes, you have a 96% chance of getting an issued patent by 3 years after the first office action. Examiner Fernandes is an extremely easy examiner and in the 4th percentile across all examiners (with 100th percentile most difficult).

Grant Rate

Grant Rate Timeline

Below is the grant rate timeline for Examiner Fernandes, where the timeline is relative to the date of the first office action. The three-year grant rate is the percentage of applications granted at three years after the first office action.

Comparison with Art Unit 2893

Examiner Fernandes's grant rate is higher than that of Art Unit 2893 and higher than that of the USPTO.

Average Office Actions Per Grant
Examiner Fernandes 0.8
Art Unit 2893 1.3

Interview Benefit

Grant Rate without Interview

Examiner Fernandes has granted 417 of 434 cases without any applicant-requested interviews for a grant rate of 96%.

Grant Rate with Interview

Examiner Fernandes has granted 50 of 50 cases with at least one applicant-requested interview for a grant rate of 100%.

Interview Benefit

With Examiner Fernandes, conducting an interview increases your chance of getting a patent granted by 4%.

Recent Dispositions

Recent Dispositions

Number Title OA Rejections Status IFW
18119784 Semiconductor Device Package And Method Of Manufacturing The Same Rejection information available with a Premium Stats subscription. See our pricing. Patented View
17652542 Methods For Assembling Stacked Substrate Packages Including Dies, Laminated Base Substrates, And Dielectric Build-Up Substrates Patented View
17892821 Semiconductor Device And Method Forming Same Patented View
17710912 Flip Chip Package For Semiconductor Devices Patented View
18498621 Display Panel And Preparation Method Of Display Panel Patented View
18922192 Semiconductor Die Assemblies With Decomposable Materials And Associated Methods And Systems Patented View
18788822 Wire Bonding Method And Apparatus For Electromagnetic Interference Shielding Patented View
18929113 Vertical Memory Devices Patented View
18322735 Interposer With Built-In Wiring For Testing An Embedded Integrated Passive Device And Methods For Forming The Same Patented View
18448957 Semiconductor Device, Semiconductor Package And Manufacturing Method Thereof Patented View
18232617 Semiconductor Package Patented View
17891665 Template Structure For Quasi-Monolithic Die Architectures Patented View
18201319 Semiconductor Structure And Method For Arranging Redistribution Layer Of Semiconductor Device Patented View
17889163 Package Comprising A First Substrate, A Second Substrate And An Electrical Device Coupled To A Bottom Surface Of The Second Substrate Patented View
18334434 Electronic Package And Manufacturing Method Thereof Patented View
18121769 Fan-Out Packaging Device Using Bridge And Method Of Manufacturing Fan-Out Packaging Device Using Bridge Patented View
18202375 Semiconductor Package Patented View
18060573 Semiconductor Package And Manufacturing Method Thereof Patented View
17854613 Microelectronic Assemblies Including Stacked Dies Coupled By A Through Dielectric Via Patented View
17890210 Semiconductor Device Patented View
17704061 Multichip Interconnect Package Fine Jet Underfill Patented View
17696258 Semiconductor Devices And Data Storage Systems Including The Same Patented View
17975455 Electronic Package And Manufacturing Method Thereof Patented View
17723954 Integrated Passive Device Dies And Methods Of Forming And Placement Of The Same Patented View
17934135 Semiconductor Device Patented View
18049428 Semiconductor Package Including Underfill And Method Of Forming The Same Patented View
17899522 Substrates With Spacers, Including Substrates With Solder Resist Spacers, And Associated Devices, Systems, And Methods Patented View
17831492 Display Apparatus Patented View
18209500 Package Structure And Manufacturing Method Thereof Patented View
17888293 Chip Package With Core Embedded Integrated Devices Patented View
17942149 Multichip Interconnect Package Patented View
17804971 Work-Function Layers In The Gates Of Pfets Patented View
18050705 Semiconductor Package Patented View
18416180 Overlapping Die Stacks For Nand Package Architecture Patented View
18489814 Semiconductor Package Structure Patented View
17730410 Buffer Block Structures For C4 Bonding And Methods Of Using The Same Patented View
18165419 Semiconductor Package Including A Plurality Of Semiconductor Chips Patented View
17712339 Microelectronic Assemblies Patented View
17975692 Semiconductor Package Patented View
17890834 Spacers For Semiconductor Device Assemblies Patented View
18492402 Package Comprising Integrated Devices And Bridge Coupling Top Sides Of Integrated Devices Patented View
18740503 Package Structure Patented View
17956566 Electronic Package And Manufacturing Method Thereof Patented View
17825042 Semiconductor Packages Including Mixed Bond Types And Methods Of Forming Same Patented View
17531133 Chip Package Structure And Chip Packaging Method Patented View
18646951 Semiconductor Package Patented View
18643144 Semiconductor Package Patented View
17903209 Semiconductor Package Patented View
17976409 Methods And Apparatus For Using Spacer-On-Spacer Design For Solder Joint Reliability Improvement In Semiconductor Devices Patented View
17678075 Package Assembly Including A Package Lid Having An Inner Foot And Methods Of Making The Same Patented View

Appeals Statistics

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