1. Stats
  2. USPTO
  3. TC 2800
  4. Group 2810-2820
  5. Art Unit 2824
  6. Examiner Begum

Examiner Begum Sultana

2824-BEGUM-SULTANA

Employment Information

Art Unit:2824 — Static information storage and retrieval
Group:2810-2820 — Semiconductors A/Memory
Classes: 365 — Static information storage and retrieval
700 — Data processing: generic control systems or specific applications
711 — Electrical computers and digital processing systems: memory
706 — Data processing: artificial intelligence
708 — Electrical computers: arithmetic processing and calculating
375 — Pulse or digital communications
257 — Active solid-state devices (e.g., transistors, solid-state diodes)
429 — Chemistry: electrical current producing apparatus, product, and process
712 — Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)
Phone:(571) 431-0691
Email:sultana.begum@uspto.gov
Location:VA 22314
Title:Pat Examnr Elctrl Engrg
Service:11 years
Grade:GS-14

Grant Rate and Difficulty Ranking

6
3-Year Grant rate: 95% over 347 cases
Difficulty: Extremely Easy
Difficulty Percentile: 6th

With Examiner Begum, you have a 95% chance of getting an issued patent by 3 years after the first office action. Examiner Begum is an extremely easy examiner and in the 6th percentile across all examiners (with 100th percentile most difficult).

Grant Rate

Grant Rate Timeline

Below is the grant rate timeline for Examiner Begum, where the timeline is relative to the date of the first office action. The three-year grant rate is the percentage of applications granted at three years after the first office action.

Comparison with Art Unit 2824

Examiner Begum's grant rate is lower than that of Art Unit 2824 and higher than that of the USPTO.

Average Office Actions Per Grant
Examiner Begum 1.4
Art Unit 2824 1.0

Interview Benefit

Grant Rate without Interview

Examiner Begum has granted 254 of 263 cases without any applicant-requested interviews for a grant rate of 97%.

Grant Rate with Interview

Examiner Begum has granted 76 of 84 cases with at least one applicant-requested interview for a grant rate of 90%.

Interview Benefit

With Examiner Begum, conducting an interview decreases your chance of getting a patent granted by 7%.

Recent Dispositions

Recent Dispositions

Number Title OA Rejections Status IFW
18462024 Initial Setting Device Of Semiconductor Memory To Determine Valid Setting Rejection information available with a Premium Stats subscription. See our pricing. Patented View
18409292 Compact Sense Amplifier Data Latch Design With Very Low Voltage Transistors Abandoned View
18740400 Memory Device Having Non-Uniform Refresh Patented View
18408608 Semiconductor Memory Device With Sense Amplifier That Operates For Two Different Voltage Range And Writing Method Thereof Patented View
18662945 Level-Based Data Refresh In A Memory Sub-System Patented View
18436422 Power Gating Circuit With Memory Precharge Support Patented View
18397984 Apparatuses And Methods For A Multi-Bit Duty Cycle Monitor Patented View
18385256 Determination Of A Bias Voltage To Apply To One Or More Memory Cells Patented View
18341607 Semiconductor Device For Detecting Defect In Word Line Driver Patented View
18528451 Word Line Charge Integration Patented View
18744776 Memory Device With High Content Density And Encoding Method Thereof Patented View
18419959 Receiver, Operation Method Thereof, And Memory Device Patented View
18361523 Integrated Circuit With Asymmetric Arrangements Of Memory Arrays Patented View
18524136 Single-Loop Memory Device, Double-Loop Memory Device, And Zq Calibration Method Patented View
18384249 Memory Device And Memory System For Performing Resistor Offset Calibration Training Patented View
18153843 Memory Device Having Multiple Subblocks, Operating Method Thereof, And Memory System Patented View
18454104 Refresh Address Counting Circuit And Method, Refresh Address Read-Write Circuit And Electronic Device Patented View
18583267 Apparatus Operating In Geardown Mode Patented View
18230371 Channel Pre-Charge Process For Memory Devices Using Hole Pre-Charge Operation Patented View
18452518 Counting Control Circuit , Method For Counting Control Circuit And Semiconductor Memory With Counting Control Circuit Patented View
18227139 Efficient Periodic Backend Refresh Reads For Reducing Bit Error Rate In Memory Devices Patented View
18343007 Adaptive Refresh Rate Generator Patented View
18475246 Calibration Apparatus And Calibration Method Of Memory Device With Strong-Arm Comparator Patented View
18364060 Memory With Arrays Of Sense Amplifiers And Two Error Checking And Correction (Ecc) Modules Patented View
18635370 Memory Device And Operation Method With Optimized Read Level Patented View
18368158 Conductance Modulation In Computational Memory Patented View
18607646 Bitline Sense Amplifier With Equalizing Transistor And A Memory Device Patented View
18179265 Memory Device With Memory Array Connected To Circuits In Different Stacked Substrates Patented View
17291021 Semiconductor Device Sensor Unit Patented View
18325698 System And Method For Coordinated Motion Among Heterogeneous Devices Patented View
18525403 Repair Techniques For Coupled Memory Dies Patented View
18331012 Stacked Integrated Circuit Patented View
18448340 Circuit For Calibration Control, Electronic Device And Method For Calibration Control Patented View
18177756 Memory Device And Memory System With Table To Determine Refresh Timing Patented View
18179976 Semiconductor Memory Device With Plurality Of Arrays Patented View
18735715 Resistive Memory Device With Protrusion Covered With Resistance Changing Element And Method For Manufacturing The Same Patented View
18334962 Voltage Supply Structure For Memory Cell Capable Of Securing Area Margin, Semiconductor Apparatus Including The Same, And Operating Method Of The Semiconductor Apparatus Patented View
18449060 Signal Sampling Circuit With Commands/address Signal Divided Into Odd And Even Signals And Semiconductor Memory Patented View
18490240 Low Dropout Regulator, Clock Generating Circuit, And Memory Device Patented View
18474214 Circuit With Logical Function Of Computing-In-Memory, Memory Device, And Method Thereof Patented View
18155547 Latch Type Sense Amplifier For Testing Patented View
18355352 Apparatus And Method For Selectively Reducing Charge Pump Speed During Erase Operations Patented View
18477421 Techniques For Performing Write Training On A Dynamic Random-Access Memory Patented View
18295087 Memory System For Controlling Heterogeneous Clock Signal Delay Modes, Method Of Operating The Memory System, And Memory Controller Patented View
18109234 Memory And Memory System With Both Long And Short Sub Word Lines Connected To Same Row Patented View
17987555 Memory Device And Operating Method With Negativevoltage Application Abandoned View
18660338 Far End Driver For Memory Clock Patented View
18324164 Semiconductor Device And Operating Method With Page Buffer Including Latches Patented View
18364026 Memory Device And Zq Calibration Method Patented View
18025399 Memory Packaged Chip And Signal Processing Method Therefor Patented View

Appeals Statistics

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