Examiner Swanson Walter H

2815-SWANSON-WALTER-H

Employment Information

Art Unit:2815 — Active solid-state devices (e.g., transistors, solid-state diodes)
Group:2810-2820 — Semiconductors A/Memory
Classes: 257 — Active solid-state devices (e.g., transistors, solid-state diodes)
438 — Semiconductor device manufacturing: process
137 — Fluid handling
365 — Static information storage and retrieval
374 — Thermal measuring and testing
700 — Data processing: generic control systems or specific applications
165 — Heat exchange
Phone:(571) 270-3322
Email:walter.swanson@uspto.gov
Location:VA 22314
Title:Pat Examnr Gen Engrg
Service:19 years
Grade:GS-14

Grant Rate and Difficulty Ranking

31
3-Year Grant rate: 86% over 386 cases
Difficulty: Easier
Difficulty Percentile: 31st

With Examiner Swanson, you have a 86% chance of getting an issued patent by 3 years after the first office action. Examiner Swanson is an easier examiner and in the 31st percentile across all examiners (with 100th percentile most difficult).

Grant Rate

Grant Rate Timeline

Below is the grant rate timeline for Examiner Swanson, where the timeline is relative to the date of the first office action. The three-year grant rate is the percentage of applications granted at three years after the first office action.

Comparison with Art Unit 2815

Examiner Swanson's grant rate is higher than that of Art Unit 2815 and higher than that of the USPTO.

Average Office Actions Per Grant
Examiner Swanson 1.0
Art Unit 2815 1.5

Interview Benefit

Grant Rate without Interview

Examiner Swanson has granted 253 of 292 cases without any applicant-requested interviews for a grant rate of 87%.

Grant Rate with Interview

Examiner Swanson has granted 79 of 94 cases with at least one applicant-requested interview for a grant rate of 84%.

Interview Benefit

With Examiner Swanson, conducting an interview decreases your chance of getting a patent granted by 3%.

Recent Dispositions

Recent Dispositions

Number Title OA Rejections Status IFW
18191248 Semiconductor Package Including Stacked Semiconductor Devices And Method Of Manufacturing The Semiconductor Package Rejection information available with a Premium Stats subscription. See our pricing. Patented View
18012917 Buried Signal Wires For Memory Applications Patented View
18166460 Semiconductor Package And Manufacturing Method Thereof Patented View
17857332 Substrate And Method Of Manufacturing Substrate Patented View
18748475 Vertical Static Random Access Memory And Method Of Fabricating Thereof Patented View
18160818 Semiconductor Device Package With Vertically Stacked Passive Component Patented View
18737611 Mems And Nems Structures Patented View
18132581 Pop Structure Of Three-Dimensional Fan-Out Memory And Packaging Method Thereof Patented View
17835340 Heat Treatment Apparatus And Heat Treatment Method Patented View
18003345 Semiconductor Device And Method For Producing Same Patented View
18208510 Semiconductor Device And Method For Manufacturing The Same Patented View
18119118 Semiconductor Packages Including A Package Body With Grooves Formed Therein Patented View
17954633 Semiconductor Structure And Method For Preparing Semiconductor Structure Patented View
18149121 Sensor Package Patented View
17735732 Wet-Dry Bilayer Resist Patented View
17813825 Semiconductor Package With Hybrid Wire Bond And Bump Bond Connections Patented View
17901667 Semiconductor Manufacturing Device And Method For Manufacturing Semiconductor Device Abandoned View
18380053 Package-On-Package Assembly With Wire Bonds To Encapsulation Surface Patented View
18256160 Semiconductor Apparatus Patented View
18057223 Semiconductor Module Patented View
18161126 Semiconductor Structure And Manufacturing Method Of Semiconductor Structure Patented View
18361899 Integrated Circuit And Method For Manufacturing The Same Patented View
17901727 Methods For Forming Semiconductor Devices Using Metal Hardmasks Patented View
19191370 Formation Of An Array Of Nanostructures Patented View
17975394 Semiconductor Device Manufacturing Method And Semiconductor Device Abandoned View
17941331 Double Patterning Method Of Patterning A Substrate Patented View
18053451 High Density Static Random-Access Memory Patented View
17536999 Interconnect For Ic Package Patented View
18162489 Semiconductor Package Patented View
17749023 Apparatus And Method Of Manufacturing A Display Device Patented View
18161124 Semiconductor Structure And Method For Manufacturing Same Patented View
17954350 Semiconductor Structure And Manufacturing Method Thereof Patented View
18603246 Semiconductor Structure, Method For Fabricating Thereof, And Method For Fabricating Semiconductor Layout Patented View
18740603 Semiconductor Device Patented View
18405040 Semiconductor Device Structure And Method For Forming The Same Patented View
17487150 Material For Forming Organic Film, Substrate For Manufacturing Semiconductor Device, Method For Forming Organic Film, Patterning Process, And Compound For Forming Organic Film Patented View
17860052 Semiconductor Structure And Method Of Manufacturing The Same Patented View
17989557 Methods For Preparing Small Features On A Substrate Patented View
18543799 Semiconductor Device And Method Patented View
17846040 Inspection Method And Etching System Patented View
18740444 Ic Package With Heat Spreader Patented View
18957406 Formation Of An Array Of Nanostructures Patented View
17982045 Interconnect Structure In Semiconductor Devices Patented View
17830618 Semiconductor Structure And Manufacturing Method Thereof Patented View
17584126 Precursor Delivery System And Method For Cyclic Deposition Patented View
17735289 Method For Controlling Etching Tool Patented View
17508144 Correcting Apparatus Of Extreme Ultraviolet (Euv) Photomask And Correcting Method Of Euv Photomask Patented View
18134858 Semiconductor Device And Method Of Fabricating Same Patented View
17893425 Method For Measuring Stitching Overlay Accuracy Of Image Sensor Stitching Manufacturing Patented View
17747423 Semiconductor Device And Method Of Fabricating The Same Patented View

Appeals Statistics

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