1. Stats
  2. USPTO
  3. TC 2800
  4. Group 28XX
  5. Art Unit 2898
  6. Examiner Hoang

Examiner Hoang Tuan A

2898-HOANG-TUAN-A

Employment Information

Art Unit:2898 — Active solid-state devices (e.g., transistors, solid-state diodes)
Group:28XX — Semiconductors B
Classes: 257 — Active solid-state devices (e.g., transistors, solid-state diodes)
438 — Semiconductor device manufacturing: process
374 — Thermal measuring and testing
244 — Aeronautics and astronautics
365 — Static information storage and retrieval
Phone:(571) 270-0406
Email:tuan.hoang2@uspto.gov
Location:VA 22314
Title:Patent Examiner(Materials Engineer)
Service:12 years
Grade:GS-14

Grant Rate and Difficulty Ranking

52
3-Year Grant rate: 76% over 287 cases
Difficulty: Medium
Difficulty Percentile: 52nd

With Examiner Hoang, you have a 76% chance of getting an issued patent by 3 years after the first office action. Examiner Hoang is a medium examiner and in the 52nd percentile across all examiners (with 100th percentile most difficult).

Grant Rate

Grant Rate Timeline

Below is the grant rate timeline for Examiner Hoang, where the timeline is relative to the date of the first office action. The three-year grant rate is the percentage of applications granted at three years after the first office action.

Comparison with Art Unit 2898

Examiner Hoang's grant rate is lower than that of Art Unit 2898 and lower than that of the USPTO.

Average Office Actions Per Grant
Examiner Hoang 2.1
Art Unit 2898 1.3

Interview Benefit

Grant Rate without Interview

Examiner Hoang has granted 129 of 185 cases without any applicant-requested interviews for a grant rate of 70%.

Grant Rate with Interview

Examiner Hoang has granted 89 of 102 cases with at least one applicant-requested interview for a grant rate of 87%.

Interview Benefit

With Examiner Hoang, conducting an interview increases your chance of getting a patent granted by 24%.

Recent Dispositions

Recent Dispositions

Number Title OA Rejections Status IFW
17999393 Semiconductor Device Rejection information available with a Premium Stats subscription. See our pricing. Abandoned View
18178665 Method Of Self-Aligned Dielectric Wall Formation For Forksheet Application Patented View
18349617 Semiconductor Device With Varying Numbers Of Channel Layers And Method Of Fabrication Thereof Patented View
18150266 Composite Gate Dielectric For High-Voltage Device Patented View
18063859 Vertically Stacked Transistor Structures Patented View
17848605 Semiconductor Device And Method Patented View
18106540 Integrated Circuit Device Patented View
18229682 Semiconductor Device Structure And Methods Of Forming The Same Patented View
17455938 Forksheet Transistor Device With Air Gap Spine Patented View
18364352 Multilayer Masking Layer And Method Of Forming Same Patented View
18192146 Semiconductor Device And Manufacturing Method Thereof Patented View
17795572 Display Substrate And Manufacturing Method Thereof, Display Module, And Display Apparatus Patented View
18077203 Transistor With Fin Structure And Nanosheet And Fabricating Method Of The Same Patented View
17832866 Seal Ring For Semiconductor Device With Gate-All-Around Transistors Patented View
17459784 Semiconductor Devices And Methods Of Manufacturing Thereof Patented View
18109205 Semiconductor Device Structure And Methods Of Forming The Same Patented View
18063991 Method For Forming A Semiconductor Device Patented View
18357464 Multi-Gate Device And Related Methods Patented View
17884773 Method Of Manufacturing A Replacement Metal Gate Device Structure Patented View
18123653 Semiconductor Devices Patented View
18348818 Semiconductor Device And Method For Forming The Same Patented View
18162350 Method For Forming Semiconductor Structure Patented View
18151481 Transistor And Semiconductor Device With Multiple Threshold Voltages And Fabrication Method Thereof Patented View
18072784 Semiconductor Devices Having Spacer Structures Patented View
18061688 Gate Dielectric Having A Non-Uniform Thickness Profile Patented View
18357795 Method For Forming Semiconductor Device Patented View
18344441 Semiconductor Device And Method Patented View
18065353 Method For Forming A Stacked Fet Device Patented View
18134117 Metal Oxide And Semiconductor Device Patented View
18161219 Ic Device With Vertically-Graded Silicon Germanium Region Adjacent Device Channel And Method For Forming Patented View
18168294 Gate-All-Around Devices With Optimized Gate Spacers And Gate End Dielectric Patented View
17744088 Methods For Forming Pattern Layout, Mask, And Semiconductor Structure Patented View
17446479 Strain Generation And Anchoring In Gate-All-Around Field Effect Transistors Patented View
17887320 Method For Manufacturing Semiconductor Device Patented View
17722572 Display Apparatus And Method Of Manufacturing The Same Patented View
17856157 Semiconductor Devices Patented View
17874295 Transistor Gate Profile Optimization Patented View
17875468 High-Voltage Nano-Sheet Transistor Patented View
18158036 Air Spacer And Capping Structures In Semiconductor Devices Patented View
18297824 Dielectric Inner Spacers In Multi-Gate Field-Effect Transistors Patented View
17382859 Semiconductor Devices And Methods Of Manufacturing Thereof Patented View
17892827 Bulk Nanosheet With Dielectric Isolation Patented View
16713619 Co-Integrated High Performance Nanoribbon Transistors With High Voltage Thick Gate Finfet Devices Patented View
17852806 Alignment Structure For Semiconductor Device And Method Of Forming Same Patented View
17874022 Gate-All-Around Devices With Optimized Gate Spacers And Gate End Dielectric Patented View
17463019 Forming Dielectric Sidewall And Bottom Dielectric Isolation In Fork-Fet Devices Patented View
17814282 Air Spacer Formation For Semiconductor Devices Patented View
18102928 Semiconductor Device Structure And Methods Of Forming The Same Patented View
17881866 Semiconductor Devices And Methods Of Manufacture Patented View
18071467 Device, Method And System To Provide A Stressed Channel Of A Transistor Patented View

Appeals Statistics

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