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| Art Unit: | 2199 — Electrical computers and digital processing systems: virtual machine task or process management or task management/control |
|---|---|
| Group: | 2190 — Interprocess Communications and Software Development |
| Classes: |
718 — Electrical computers and digital processing systems: virtual machine task or process management or task management/control 719 — Electrical computers and digital processing systems: interprogram communication or interprocess communication (ipc) 717 — Data processing: software development, installation, and management |
| Phone: | (571) 272-3759 |
| Email: | lewis.bullock@uspto.gov |
| Title: | Supvy Pat Examnr Elctrl Engrg |
| Service: | 28 years |
| Grade: | GS-15 |
| 3-Year Grant rate: | 40% over 15 cases |
|---|---|
| Difficulty: | Very Hard |
| Difficulty Percentile: | 86th
|
With Examiner Bullock (SPE), you have a 40% chance of getting an issued patent by 3 years after the first office action. Examiner Bullock (SPE) is a very hard examiner and in the 86th percentile across all examiners (with 100th percentile most difficult).
Below is the grant rate timeline for Examiner Bullock (SPE), where the timeline is relative to the date of the first office action. The three-year grant rate is the percentage of applications granted at three years after the first office action.
Examiner Bullock (SPE)'s grant rate is lower than that of Art Unit 2199 and lower than that of the USPTO.
| Average Office Actions Per Grant | |
|---|---|
| Examiner Bullock (SPE) | 2.3 |
| Art Unit 2199 | 1.7 |
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Disclaimer: We do not provide any guarantees as to the accuracy of the statistics presented above and under
no circumstances will we be liable for any outcome resulting from your reliance on the above statistics.