1. Stats
  2. USPTO
  3. TC 2100
  4. Group 2180
  5. Art Unit 2183
  6. Examiner Alli

Examiner Alli Kasim A

2183-ALLI-KASIM-A

Employment Information

Art Unit:2183 — Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)
Group:2180 — Computer Architecture, I/O, Modeling and Simulation
Classes: 712 — Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)
726 — Information security
Phone:(571) 270-1476
Email:kasim.alli@uspto.gov
Location:VA 22314
Title:Patent Examiner(Computer Engr)
Service:9 years
Grade:GS-13

Grant Rate and Difficulty Ranking

65
3-Year Grant rate: 67% over 123 cases
Difficulty: Harder
Difficulty Percentile: 65th

With Examiner Alli, you have a 67% chance of getting an issued patent by 3 years after the first office action. Examiner Alli is a harder examiner and in the 65th percentile across all examiners (with 100th percentile most difficult).

Grant Rate

Grant Rate Timeline

Below is the grant rate timeline for Examiner Alli, where the timeline is relative to the date of the first office action. The three-year grant rate is the percentage of applications granted at three years after the first office action.

Comparison with Art Unit 2183

Examiner Alli's grant rate is lower than that of Art Unit 2183 and lower than that of the USPTO.

Average Office Actions Per Grant
Examiner Alli 2.3
Art Unit 2183 1.5

Interview Benefit

Grant Rate without Interview

Examiner Alli has granted 39 of 57 cases without any applicant-requested interviews for a grant rate of 68%.

Grant Rate with Interview

Examiner Alli has granted 43 of 66 cases with at least one applicant-requested interview for a grant rate of 65%.

Interview Benefit

With Examiner Alli, conducting an interview decreases your chance of getting a patent granted by 4%.

Recent Dispositions

Recent Dispositions

Number Title OA Rejections Status IFW
18378207 Implied Fence On Stream Open Rejection information available with a Premium Stats subscription. See our pricing. Patented View
18032157 Breathing Operand Windows To Exploit Bypassing In Graphics Processing Units Abandoned View
17029335 System, Apparatus And Methods For Register Hardening Via A Micro-Operation Abandoned View
16914317 Loading And Storing Matrix Data With Datatype Conversion Abandoned View
18135481 Executing Phantom Loops In A Microprocessor Patented View
18830458 Vector Computational Unit Patented View
17699855 Load Dependent Branch Prediction Abandoned View
17965275 Store To Load Forwarding Using Hashes Patented View
18232531 Associatively Indexed Circular Buffer Patented View
18490672 Instruction Set Architecture For A Vector Computational Unit Patented View
18314655 To-Be-Executed Instruction Prediction Method And System Patented View
15192992 Scatter To Gather Operation Abandoned View
17560547 Conversion Instructions Abandoned View
17712073 Circuitry And Methods For Informing Indirect Prefetches Using Capabilities Patented View
18717956 Vector Shuffling Method, Processor And Electronic Device Patented View
17557583 Predicting Upcoming Control Flow Patented View
17814729 Using A Next Fetch Predictor Circuit With Short Branches And Return Fetch Groups Patented View
17241726 Rescheduling A Load Instruction Based On Past Replays Patented View
17033680 Circuitry And Methods For Power Efficient Generation Of Length Markers For A Variable Length Instruction Set Patented View
18336704 Dsb Operation With Excluded Region Patented View
18305173 Re-Use Of Speculative Control Transfer Instruction Results From Wrong Path Patented View
17897405 Streaming Engine With Stream Metadata Saving For Context Switching Patented View
17956034 Store Instruction Merging With Pattern Detection Patented View
17931070 Program Counter Zero-Cycle Loads Patented View
17712018 Forward Conditional Branch Event For Profile-Guided-Optimization (Pgo) Abandoned View
17693748 Generating Encrypted Capabilities Within Bounds Abandoned View
17939518 Providing Memory Prefetch Instructions With Completion Notifications In Processor-Based Devices Abandoned View
16264458 Pair Merge Execution Units For Microinstructions Patented View
17937335 Configurable Vector Compute Engine Patented View
17810253 Multi-Degree Branch Predictor Patented View
18693524 Order-Preserving Method And System For Multiple Sets Of Load Store Queues Of Processor And Related Device Patented View
17946113 Method Of Storing Register Data Elements To Interleave With Data Elements Of A Different Register, A Processor Thereof, And A System Thereof Patented View
18061205 Data Hazard Generation Patented View
17335945 Processor Supporting Position-Independent Addressing Patented View
17853790 Accelerating Predicated Instruction Execution In Vector Processors Patented View
17846030 Processor, Operation Method, And Load-Store Device For Implementation Of Accessing Vector Strided Memory Patented View
17725342 Microprocessor With Non-Cacheable Memory Load Prediction Patented View
16771376 Dynamic Processor Architecture Control Patented View
17506122 Cache Coherence Validation Using Delayed Fulfillment Of L2 Requests Patented View
17829909 Vector Coprocessor With Time Counter For Statically Dispatching Instructions Patented View
17620527 Data Processing Apparatus And Related Product Patented View
17463535 Multiple Interfaces For Multiple Threads Of A Hardware Multi-Thread Microprocessor Patented View
17807243 Load Reissuing Using An Alternate Issue Queue Patented View
17817593 Vector Computational Unit Patented View
15855637 Stream Processor With Low Power Parallel Matrix Multiply Pipeline Patented View
17704627 Array Of Pointers Prefetching Patented View
17566157 Methods And Apparatus For Tracking Instruction Information Stored In Virtual Sub-Elements Mapped To Physical Sub-Elements Of A Given Element Patented View
17835409 Dynamically Foldable And Unfoldable Instruction Fetch Pipeline Patented View
17407267 Variable Formatting Of Branch Target Buffer Patented View
17835294 Branch Target Buffer That Stores Predicted Set Index And Predicted Way Number Of Instruction Cache Patented View

Appeals Statistics

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