Examiner Rojas Midys

2133-ROJAS-MIDYS

Employment Information

Art Unit:2133 — Electrical computers and digital processing systems: memory
Group:2130 — Memory Access and Control
Classes: 711 — Electrical computers and digital processing systems: memory
714 — Error detection/correction and fault detection/recovery
365 — Static information storage and retrieval
706 — Data processing: artificial intelligence
726 — Information security
713 — Electrical computers and digital processing systems: support
Phone:(571) 272-4207
Email:midys.rojas@uspto.gov
Location:VA 22314
Title:Pat Examnr Elctrl Engrg
Service:24 years
Grade:GS-14

Grant Rate and Difficulty Ranking

9
3-Year Grant rate: 93% over 303 cases
Difficulty: Extremely Easy
Difficulty Percentile: 9th

With Examiner Rojas, you have a 93% chance of getting an issued patent by 3 years after the first office action. Examiner Rojas is an extremely easy examiner and in the 9th percentile across all examiners (with 100th percentile most difficult).

Grant Rate

Grant Rate Timeline

Below is the grant rate timeline for Examiner Rojas, where the timeline is relative to the date of the first office action. The three-year grant rate is the percentage of applications granted at three years after the first office action.

Comparison with Art Unit 2133

Examiner Rojas's grant rate is higher than that of Art Unit 2133 and higher than that of the USPTO.

Average Office Actions Per Grant
Examiner Rojas 1.2
Art Unit 2133 1.2

Interview Benefit

Grant Rate without Interview

Examiner Rojas has granted 229 of 248 cases without any applicant-requested interviews for a grant rate of 92%.

Grant Rate with Interview

Examiner Rojas has granted 53 of 55 cases with at least one applicant-requested interview for a grant rate of 96%.

Interview Benefit

With Examiner Rojas, conducting an interview increases your chance of getting a patent granted by 4%.

Recent Dispositions

Recent Dispositions

Number Title OA Rejections Status IFW
18793994 Interleaving Raid Slices Allocation For Fast Rebuild Rejection information available with a Premium Stats subscription. See our pricing. Patented View
18521309 Coordinated Storage Tiering Across Sites Patented View
18311893 Memory Device And Storage Device Including The Same Patented View
18772712 Kv Cache Block-Quantization Oriented Data Handling Patented View
19097694 Reduced Data Stored In Intent Logs Of Storage Systems Patented View
19277224 Sequential Reconstruction For Dynamic Stripe Width Raid Patented View
18778203 Storage Usage Patented View
18530263 Memory Control System And Memory Control Method Patented View
18905391 Dynamic Bifurcated Bus Width Raid Storage System Patented View
18329707 Purposed Data Transfer Using Multiple Cache Slots Patented View
18199765 Storage Device, Operation Method Of The Storage Device, And Electronic System Including The Storage Device Patented View
18908844 Memory Controller Circuit And System For Artificial Neural Network And Method Thereof Patented View
18657466 Memory Management Patented View
18790549 Converting Dix To Dif Using Hmb Buffer Management Patented View
18641623 Computing System And Transposition Method Therefor Patented View
18760043 Memory Management Method For Evenly Distributing Input Output Latency Time, Memory Storage Device, And Memory Control Circuit Unit Patented View
18639662 Early Potential Hpa Generator Patented View
17357951 Zero-Redundancy Tag Storage For Bucketed Allocators Patented View
19173788 Systems And Methods For Data Management Based On Industrial Internet Of Things (Iiot) Data Centers Patented View
18187900 Duplicating Memory Content With Chipset Attached Memory Patented View
18347190 Bandwidth Control Method And Storage Device Patented View
18731089 Alleviating Interconnect Traffic In A Disaggregated Memory System Patented View
17512432 Page Offlining Based On Fault-Aware Prediction Of Imminent Memory Error Patented View
18793079 Optical Computing With Disaggregated Memory Patented View
18589430 Integrated Circuit Data Stream Processing Using Paged Buffering Patented View
17572409 Application Programming Interface To Disassociate A Virtual Address Patented View
18494641 Memory Buffer Devices With Modal Encryption Patented View
17985710 Tuning Storage Devices Patented View
18202783 Controller Cache Architeture Patented View
18089515 Memory Device, Method For Controlling Memory Device And Memory System Patented View
17957262 Runtime Flushing To Persistency In Heterogenous Systems Patented View
18655510 Multi-Modal Refresh Of Dynamic, Random-Access Memory Patented View
18616006 Voltage Bin Calibration Based On A Voltage Distribution Reference Voltage Patented View
17733431 Using Data Volumes To Store Container Images Patented View
18670065 Mechanisms For Grouping Nodes Patented View
18099006 Method And Apparatus For Data Transfer Between Accessible Memories Of Multiple Processors In A Heterogeneous Processing System Using Two Memory To Memory Transfer Operations Patented View
18207963 Memory System Based On Flash Memory And Method For Managing Meta Data Thereof Patented View
18602472 Storage Device Patented View
18248262 Backup Recovery System And Method For Oracle Database Patented View
18584993 Apparatus With Memory Cell Calibration Mechanism And Methods For Operating The Same Patented View
18600269 Source Address Memory Managment Patented View
17869919 System And Method For Distributed Input/output (Io) Performance Forecasting Across Multiple Machine Learning Models Patented View
17733748 Storage System Based Threat Detection And Remediation For Containers Patented View
18308019 Serving Application Programming Interface Calls Directed To Hierarchical Data Format Files Stored In Fabric-Attached Memories Patented View
17092640 End-To-End Data Plane Offloading For Distributed Storage Using Protocol Hardware And Pisa Devices Patented View
18429911 Methods And Systems To Interface Between A Multi-Site Distributed Storage System And An External Mediator To Efficiently Process Events Related To Continuity Patented View
18307686 Methods And Systems For Altering The Path Of Data Movement For Large-Sized Memory Transactions Patented View
18132092 Method Of Writing Data In Storage Device Using Write Throttling And Storage Device Performing The Same Patented View
18053919 Nonvolatile Memory Device And Operation Method Thereof Patented View
18250646 Raid Optimizaiton Method For Multi-Pass Programing Nand, And Computer Device Patented View

Appeals Statistics

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