1. Stats
  2. USPTO
  3. TC 2100
  4. Group 2110
  5. Art Unit 2112
  6. Examiner Abraham

Examiner Abraham Esaw T

2112-ABRAHAM-ESAW-T

Employment Information

Art Unit:2112 — Error detection/correction and fault detection/recovery
Group:2110 — Computer Error Control, Reliability, & Control Systems
Classes: 714 — Error detection/correction and fault detection/recovery
709 — Electrical computers and digital processing systems: multicomputer data transferring
726 — Information security
706 — Data processing: artificial intelligence
370 — Multiplex communications
380 — Cryptography
Phone:(571) 272-3812
Email:esaw.abraham@uspto.gov
Location:VA 22314
Title:Pat Examnr Computer Science
Service:24 years
Grade:GS-14

Grant Rate and Difficulty Ranking

4
3-Year Grant rate: 96% over 423 cases
Difficulty: Extremely Easy
Difficulty Percentile: 4th

With Examiner Abraham, you have a 96% chance of getting an issued patent by 3 years after the first office action. Examiner Abraham is an extremely easy examiner and in the 4th percentile across all examiners (with 100th percentile most difficult).

Grant Rate

Grant Rate Timeline

Below is the grant rate timeline for Examiner Abraham, where the timeline is relative to the date of the first office action. The three-year grant rate is the percentage of applications granted at three years after the first office action.

Comparison with Art Unit 2112

Examiner Abraham's grant rate is higher than that of Art Unit 2112 and higher than that of the USPTO.

Average Office Actions Per Grant
Examiner Abraham 0.9
Art Unit 2112 1.1

Interview Benefit

Grant Rate without Interview

Examiner Abraham has granted 364 of 381 cases without any applicant-requested interviews for a grant rate of 96%.

Grant Rate with Interview

Examiner Abraham has granted 41 of 42 cases with at least one applicant-requested interview for a grant rate of 98%.

Interview Benefit

With Examiner Abraham, conducting an interview increases your chance of getting a patent granted by 2%.

Recent Dispositions

Recent Dispositions

Number Title OA Rejections Status IFW
18807215 Hamming Code Encoding And Arranging Method And Storage Device Detection Method Rejection information available with a Premium Stats subscription. See our pricing. Patented View
18766409 Buffer Circuit With Adaptive Repair Capability Patented View
18610718 Tracking Memory Defects Using A Shared Memory Defect List Patented View
18764731 Column Redundancy Circuit And Memory Device Including Same Patented View
18639692 Selective Mode Error Control Patented View
17461364 Debug Data Communication System For Multiple Chips Patented View
18415626 Heterogenous Interleaved Reed-Solomon (Hetirs) With Erasure Decoding Patented View
18804211 Memory Controllers And Storage Devices Including The Same Patented View
18643302 Error Correction Code (Ecc) Circuit Including Low-Density Parity-Check Decoder In Adaptive Operation Mode, Operating Method Of The Ecc Circuit, And Memory Controller Including The Ecc Circuit Patented View
18734882 Error Correction Decoding Device Patented View
18594795 Managing Error Control Information Using A Register Patented View
18757065 Two-Dimensional Generalized Concatenated Codes With Sub-Fields Patented View
18528945 Decoder-Assisted Llr Calculation Patented View
18545596 Low Latency Digital Rebroadcast Of Signals With Fec And Interleaving Patented View
18667799 Information Broadcast Techniques For Stacked Memory Architectures Patented View
17895761 Defective Memory Unit Screening In A Memory System Patented View
18752740 Dram Ecc Circuit Error Detection Integrity Patented View
18671810 Optimized Decoding Scheduling In A Joint Ldpc And Raid Decoding Scheme Patented View
19117645 Transmission Device, Transmission Method, Reception Device, And Reception Method Abandoned View
18604940 Memory System Generating Error Correction Code Parity Based On Rank Patented View
18664870 Permanent Defect Qubit Repair System And Method Using Built-In-Self-Repair Model At Quantum Circuit Level Patented View
18783892 Iterative Bit Flip Decoding Utilizing Different Bit Flip States Patented View
18601224 Trait Based Storage Unit Groups Patented View
18582524 Device And Methods For Managing The Data Integrity Of Read And Write Operations Patented View
18243220 Performing Quantum Error Mitigation At Runtime Using Trained Machine Learning Model Patented View
18414048 Reporting Redundancy Version With Feedback Information Patented View
18755334 Concatenated Code Encoding Method, Concatenated Code Decoding Method, And Communication Apparatus Patented View
18734486 Polar Decoder And Associated Method Patented View
18423543 Method For Transmitting A Check Vector From A Transmitter Unit To A Receiver Unit Patented View
18437158 Electronic Device For Updating Frame Error Rate Of Link And Operation Method Of Electronic Device Patented View
18346671 Storage Device For Setting Prohibited Threshold Voltage Distribution Patented View
18512436 Systems And Methods For Decoding Codewords Patented View
18499370 Nested Error Correction Codes For Dna Data Storage Patented View
18582490 System And Methods For Managing The Data Integrity Of Read And Write Operations Patented View
18446489 Peripheral Component Interconnect Express Interface Device And System Including The Same Patented View
19040282 Forward Error Correction In Digital Communication Systems Patented View
18864849 Adaptive Scaling Of Parity Check Messages For Ldpc Decoding Patented View
18487267 Error Correction With Error Code For A String Of Symbols Patented View
18620595 Coding Circuit And Memory Device Including The Same Patented View
18598832 Apparatuses, Systems, And Methods For Storing Error Information And Providing Recommendations Based On Same Patented View
18029156 Method, Device And Computer Storage Medium For Communication Patented View
18235738 Constrained Random Simulation Using Machine Learning And Bayesian Estimation Patented View
18608154 Crc Interleaving Pattern For Polar Codes Patented View
18593519 Data Interleaving Method And Data Interleaving Apparatus Patented View
18241163 Reclamation Of Memory Ecc Bits For Error Tolerant Number Formats Patented View
18629317 Systems And Methods For Blockchain Repair Assurance Tokens Patented View
18356104 Error Correction Systems And Methods For Dna Storage Patented View
18327693 Single-Shot Error Mitigation For Clifford Circuits Patented View
18142936 Flexible And Configurable Bit Error Rate Reduction For Non-Volatile Memory Patented View
18344587 Universal Fault-Tolerant Quantum Computation With A 2d Abelian Topological Stabilizer Code Using Magic Patches Patented View

Appeals Statistics

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